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V54C3128(16/80/40)4V(BGA) 128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 8M X 16 16M X 8 32M X 4
6 7PC 143 MHz 7 ns 5.4 ns 5.4 ns 166 MHz 6 ns 5.4 ns 5.4 ns
PRELIMINARY
s s s s s s
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System Frequency (fCK) Clock Cycle Time (tCK3)
7 143 MHz 7 ns 5.4 ns 6 ns
8PC 125 MHz 8 ns 6 ns 6 ns
Clock Access Time (tAC3) CAS Latency = 3 Clock Access Time (tAC2) CAS Latency = 2
Features
s s s s s 4 banks x 2Mbit x 16 organization 4 banks x 4Mbit x 8 organization 4 banks x 8Mbit x 4 organization High speed data transfer rates up to 166 MHz Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge Single Pulsed RAS Interface Data Mask for Read/Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 for Sequential Type 1, 2, 4, 8 for Interleave Type Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Random Column Address every CLK (1-N Rule) Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 4096 cycles/64 ms Available in 60 Pin WBGA LVTTL Interface Single +3.3 V 0.3 V Power Supply
Description
The V54C3128(16/80/40)4V(BGA) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4. The V54C3128(16/80/40)4V(BGA) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.
s s s s s s s s s
Device Usage Chart
Operating Temperature Range
0C to 70C
Package Outline B
*
Access Time (ns) 6
*
Power 8PC
*
7PC
*
7
*
Std.
*
L
*
Temperature Mark
Blank
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V 54
MOSEL-VITELIC MANUFACTURED SYCHRONOUS DRAM FAMILY C = CMOS PROCESS 3.3V, LVTTL, INTERFACE B = WBGA DEVICE NUMBER V = LVTTL SPECIAL FEATURE COMPONENT REV. LEVEL 8Mbit x 16: 128164 16Mbit x 8: 128804 32Mbit x 4: 128404 PKG.
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Description WBGA Pkg. B Pin Count 60
C
3
128404
V
B
SPEED 6 ns 7 ns 8 ns
60 Pin WBGA PIN CONFIGURATION Top View
987 A B C D E F G H J K L M 321
9
VCCQ DQ1 DQ3 DQ5 DQ7 NC
8
DQ0 VSSQ VCCQ VSSQ NC VCC CAS CS BA0 A10/AP A1 A3
7
VCC DQ2 DQ4 DQ6 NC LDQM WE RAS BA1 A0 A2 VCC
x16
A B C D E F G H J K L M
3
VSS DQ13 DQ11 DQ9 NC UDQM NC CKE A9 A7 A5 VSS
2
DQ15 VCCQ VSSQ VCCQ NC VSS CLK A12 A11 A8 A6 A4
1
VSSQ DQ14 DQ12 DQ10 DQ8 Vref
9
VCCQ NC NC NC NC NC
8
DQ1 VSSQ VCCQ VSSQ NC VCC CAS CS BA0 A10/AP A1 A3
7
VCC DQ1 DQ2 DQ3 NC NC WE RAS BA1 A0 A2 VCC
x8
A B C D E F G H J K L M
3
VSS DQ6 DQ5 DQ4 NC DQM NC CKE A9 A7 A5 VSS
2
DQ7 VCCQ VSSQ VCCQ NC VSS CLK A12 A11 A8 A6 A4
1
VSSQ NC NC NC NC Vref
9
VCCQ NC NC NC NC NC
8
NC VSSQ VCCQ VSSQ NC VCC CAS CS BA0 A10/AP A1 A3
7
VCC DQ0 NC DQ1 NC NC WE RAS BA1 A0 A2 VCC
x4
A B C D E F G H J K L M
3
VSS DQ3 NC DQ2 NC DQM NC CKE A9 A7 A5 VSS
2
NC VCCQ VSSQ VCCQ NC VSS CLK A12 A11 A8 A6 A4
1
VSSQ NC NC NC NC Vref
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Absolute Maximum Ratings*
Max. Unit
3.8 3.8 pF pF
Block Diagram
Column decoder Sense amplifier & I(O) bus
Bank 0
Column decoder Sense amplifier & I(O) bus
Bank 1
Column decoder Sense amplifier & I(O) bus
Bank 2
Column decoder Sense amplifier & I(O) bus
WE
LDQM
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UDQM
CKE
RAS
CLK
CAS
CS
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Capacitance*
Symbol C I1 C I2 C IO C CLK
TA = 0 to 70C, VCC = 3.3 V 0.3 V, f = 1 Mhz
Parameter Input Capacitance (A0 to A11) Input Capacitance RAS, CAS, WE, CS, CLK, CKE, DQM Output Capacitance (I/O) Input Capacitance (CLK)
Operating temperature range .................. 0 to 70 C Storage temperature range ................-55 to 150 C Input/output voltage.................. -0.3 to (VCC+0.3) V Power supply voltage .......................... -0.3 to 4.6 V Power dissipation ..............................................1 W Data out current (short circuit).......................50 mA
*Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6 3.5
pF pF
*Note:Capacitance is sampled and not 100% tested.
x16 Configuration
Column Addresses A0 - A8, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1
Column address counter
Column address buffer
Row address buffer
Refresh Counter
Row decoder Memory array
Row decoder Memory array
Row decoder Memory array
Row decoder Memory array Bank 3
4096 x 512 x 16 bit
4096 x 512 x16 bit
4096 x 512 x 16 bit
4096 x 512 x 16 bit
Input buffer
Output buffer
Control logic & timing generator
I/O1-I/O16
V54C3128(16/80/40)4V(BGA)
x8 Configuration
Column Addresses A0 - A9, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1
Block Diagram
Column decoder Sense amplifier & I(O) bus
Column decoder Sense amplifier & I(O) bus
Column decoder Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder Sense amplifier & I(O) bus
CKE
RAS
CAS
WE
CS
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DQM
CLK
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Column address counter Column address buffer Row decoder Memory array Row decoder Memory array 4096 x 1024 x 8 bit 4096 x 1024 x 8 bit Input buffer Output buffer I/O1-I/O8
Row address buffer
Refresh Counter
Row decoder Memory array
Row decoder Memory array Bank 3
4096 x 1024 x 8 bit
4096 x 1024 x 8 bit
Control logic & timing generator
V54C3128(16/80/40)4V(BGA)
x4 Configuration
Column Addresses A0 - A9, A11, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1
Block Diagram
Column decoder Sense amplifier & I(O) bus
Column decoder Sense amplifier & I(O) bus
Column decoder Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder Sense amplifier & I(O) bus
CAS
RAS
CKE
WE
CS
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DQM
CLK
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Column address counter Column address buffer Row decoder Memory array Row decoder Memory array 4096 x 2048 x 4 bit 4096 x 2048 x 4 bit Input buffer Output buffer I/O1-I/O4
Row address buffer
Refresh Counter
Row decoder Memory array
Row decoder Memory array Bank 3
4096 x 2048 x 4 bit
4096 x 2048 x 4 bit
Control logic & timing generator
V54C3128(16/80/40)4V(BGA)
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Pin
CLK
Signal Pin Description
Type
Input
Signal
Pulse
Polarity
Positive Edge
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode or the Self Refresh mode. Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. -- During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organization: * 32M x 4 SDRAM CA0-CA9, CA11. * 16M x 8 SDRAM CA0-CA9. * 8M x 16 SDRAM CA0-CA8. In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are used to define which bank to precharge.
CS
Input
Pulse
RAS, CAS WE A0 - A11
Input
Pulse
Input
Level
BA0, BA1 DQx
Input
Level
--
Selects which bank is to be active.
Input Output Input
Level
--
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM UDQM
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Power and ground for the input buffers and the core logic.
VCC, VSS Supply VCCQ VSSQ Supply -- --
Isolated power supply and ground for the output buffers to provide improved noise immunity.
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All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate Read Read w/Autoprecharge Write Write with Autoprecharge Row Precharge Precharge All Mode Register Set No Operation Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit
Notes: 1. V = Valid , x = Don't Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. These are state of bank designated by BS0, BS1 signals. 4. Power Down Mode can not entry in the burst cycle.
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Operation Definition
Device State
Idle3 Active3 Active
3
CKE n-1
H H H H H H H H H H H H
CKE n
X X X X X X X X X X H L
CS
L L L L L L L L L H L L H
RAS
L H H H H L L L H X L L X H X H X H X X
CAS
H L L L L H H L H X L L X H X H X H X X
WE
H H H L L L L L H X H H X X X X X L X X
DQM
X X X X X X X X X X X X
A0-9, A11
V V V V V X X V X X X X
A10
V L H L H L H V X X X X
BS0 BS1
V V V V V V X V X X X X
Active3 Active3 Any Any Idle Any Any Idle Idle Idle (Self Refr.) Idle Active4 Any (Power Down) Active Active
L
H
L H
X
X
X
X
Power Down Entry
H
L
L H
X
X
X
X
Power Down Exit
L
H
L X X
X
X
X
X
Data Write/Output Enable Data Write/Output Disable
H H
X X
L H
X X
X X
X X
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operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table.
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VCC and VCCQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 s is required followed by a precharge of both banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set
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Power On and Initialization
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Programming the Mode Register
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Address Input for Mode Set (Mode Register Operation)
Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies
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0 0 0 0 0 0
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register
Operation Mode
BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 Mode Burst Read/Burst Write Burst Read/Single Write
Burst Type
A3 0 1 Type Sequential Interleave
0
1
0
0
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 Reserve Reserve Reserve Reserve
Burst Length
Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 Sequential 0 1 0 1 0 1 0 1 1 2 4 8 Reserve Reserve Reserve Reserve Interleave 1 2 4 8 Reserve Reserve Reserve Reserve
with an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be done between different pages.
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2 4 xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 8
Burst Length and Sequence:
Burst Starting Address Length (A2 A1 A0) Sequential Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3, 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 1, 2, 3, 0, 3 4 5 6 7 0 1 2 2, 3, 0, 1, 4 5 6 7 0 1 2 3 3 0 1 2 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 0, 1, 2, 3, Interleave Burst Addressing (decimal) 0, 1 1, 0 1, 0, 3, 2, 3 2 1 0 7 6 5 4 2, 3, 0, 1, 4 5 6 7 0 1 2 3 3 2 1 0 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command.
a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE "high". One clock delay is required for mode entry and exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latencies 2, two clocks for CAS latencies 3 and three clocks for CAS latencies 4. If CA10 is high when a Write Command is issued, the Write
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to "high" at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ ). It also provides
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Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the I/O pins before the Burst Stop Command is registered will be written to the memory.
with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in.
There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS latency = 3. Writes require a time delay twr from the last data out to apply the precharge command. Bank Selection by Address Bits:
A10 0 0 0 0 1 BA0 BA1 0 0 1 1 X 0 1 0 1 X Bank 0 Bank 1 Bank 2 Bank 3 all Banks
Note: 1. All voltages are referenced to VSS. 2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
CILETIV LESOM
Parameter
Input high voltage Input low voltage
Precharge Command
Recommended Operation and Characteristics for LV-TTL
TA = 0 to 70 C; VSS = 0 V; VCC,VCCQ = 3.3 V 0.3 V
Limit Values Symbol
VIH VIL VOH VOL II(L) IO(L)
min.
2.0 - 0.3 2.4 - -5
max.
Vcc+0.3 0.8 - 0.4 5
Unit
V V V V A A
Notes
1, 2 1, 2
Output high voltage (IOUT = - 4.0 mA) Output low voltage (IOUT = 4.0 mA) Input leakage current, any input (0 V < V IN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC )
-5
5
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Notes: 7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 8. These parameter depend on output loading. Specified values are obtained with output open.
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Symbol
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P ICC4 ICC5 ICC6
Operating Currents (TA = 0 to 70C, VCC = 3.3V 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Max. Parameter & Test Condition
Operating Current tRC = tRCMIN., tRC = tCKMIN . Active-precharge command cycling, without Burst Operation Precharge Standby Current in Power Down Mode CS =VIH, CKE VIL(max) Precharge Standby Current in Non-Power Down Mode CS =VIH, CKE VIL(max) No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) 1 bank operation
-6
190
-7 / -7PC
170
-8PC
150
Unit
mA
Note
7
tCK = min. tCK = Infinity tCK = min. tCK = Infinity CKE VIH(MIN.) CKE VIL(MAX.) (Power down mode)
1.5 1 55 5 65
1.5 1 45 5 55
1.5 1 35 5 45
mA mA mA mA mA
7 7
10
10
10
mA
Burst Operating Current tCK = min Read/Write command cycling Auto Refresh Current tCK = min Auto Refresh command cycling Self Refresh Current Self Refresh Mode, CKE0.2V
130
110
90
mA
7,8
270
250
210
mA
7
1.5 L-version 800
1.5 800
1.5 800
mA A
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# Symbol Clock and Clock Enable
1 tCK 2 tCK 3 tAC 4 5 6 tCH tCL tT
AC Characteristics 1,2, 3
TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns
Limit Values -6 Parameter -7PC -7 -8PC
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Clock Cycle Time CAS Latency = 3 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition Tim
6 7.5
- -
7 7.5
- -
7 10
- -
8 10
- -
s ns ns
- -
166 133
- -
143 133
- -
143 100
- -
125 100
MHz MHz 2, 4
- _ 2.5 2.5 0.3
5.4 5.4 - - 1.2
- _ 2.5 2.5 0.3
5.4 5.4 - - 1.2
- _ 2.5 2.5 0.3
5.4 6 - - 1.2
- _ 3 3 0.5
6 6 - - 10
ns ns ns ns ns
Setup and Hold Times
7 8 9 10 11 12 tIS tIH tCKS tCKH tRSC tSB Input Setup Time Input Hold Time Input Setup Time CKE Hold Time Mode Register Set-up Time Power Down Mode Entry Time 1.5 0.8 1.5 0.8 12 0 - - - - - 6 1.5 0.8 1.5 0.8 14 0 - - - - - 7 1.5 0.8 1.5 0.8 14 0 - - - - - 7 2 1 2 1 16 0 - - - - - 8 ns ns ns ns ns ns 5 5 5 5
Common Parameters
13 14 15 16 17 18 tRCD tRP tRAS tRC tRRD tCCD Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command Period CAS(a) to CAS(b) Command Period 12 15 40 60 12 1 - - 100K - - - 15 15 42 60 14 1 - - 100K - - - 15 15 42 60 14 1 - - 100K - - - 20 20 45 60 16 1 - - 100k - - - ns ns ns ns ns CLK 6 6 6 6 6
Refresh Cycle
19 20 tREF tSREX Refresh Period (4096 cycles) Self Refresh Exit Time
--
64
--
--
64
--
--
64
--
--
64
--
ms CLK
1
1
1
1
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
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V54C3128(16/80/40)4V(BGA)
CILETIV LESOM
# Symbol Read Cycle
21 22 23 24 tOH tLZ tHZ tDQZ
AC Characteristics (Cont'd)
Limit Values -6 Parameter -7PC -7 -8PC
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
3 1 3 -
- - 6 2
3 1 3 -
- - 7 2
3 1 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns CLK
2
7
Write Cycle
25 26 tWR tDQW Write Recovery Time DQM Write Mask Latency 2 0 - - 2 0 - - 2 0 - - 2 0 - - CLK CLK
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet. 2. AC timing tests have VIL = 0.8V and V IH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown in Figure 1.
tCK VIH CLK VIL
+ 1.4 V 50 Ohm
tT
tCS COMMAND tCH 1.4V
Z=50 Ohm
tAC tLZ tOH tAC
I/O 50 pF
1.4V
OUTPUT tHZ
Figure 1.
4. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 5. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
14
V54C3128(16/80/40)4V(BGA)
CILETIV LESOM
Timing Diagrams
1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. Burst Termination 8.1 Termination of a Burst Write Operation 8.2 Termination of a Burst Write Operation 9. AC- Parameters 9.1 AC Parameters for a Write Timing 9.2 AC Parameters for a Read Timing 10. Mode Register Set 11. Power on Sequence and Auto Refresh (CBR) 12. Power Down Mode 13. Self Refresh (Entry and Exit) 14. Auto Refresh (CBR)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
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V54C3128(16/80/40)4V(BGA)
15. Random Column Read ( Page within same Bank) 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst 19.1 CAS Latency = 2 19.2 CAS Latency = 3
CILETIV LESOM
Timing Diagrams (Cont'd)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
16
V54C3128(16/80/40)4V(BGA)
2. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
CAS latency = 2
tCK2, I/O's
CAS latency = 3
tCK3, I/O's
CILETIV LESOM
1. Bank Activate Command Cycle (CAS latency = 3)
T0 CLK
..........
T1
T
T
T
T
T
ADDRESS
Bank A Row Addr.
Bank A Col. Addr.
..........
Bank B Row Addr.
Bank A Row Addr.
tRCD
tRRD
NOP Write A with Auto Precharge .......... Bank B Activate NOP Bank A Activate
COMMAND
: "H" or "L"
Bank A Activate
NOP
tRC
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
17
V54C3128(16/80/40)4V(BGA)
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
CILETIV LESOM
T0 CLK COMMAND
READ A CAS latency = 2
3. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCK3, I/O's
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
DQM
tDQZ
tDQW
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
I/O's
: "H" or "L"
DOUT A0 Must be Hi-Z before the Write Command
DIN B0
DIN B1
DIN B2
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
18
V54C3128(16/80/40)4V(BGA)
4.3 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK
tDQW
CILETIV LESOM
T0 CLK DQM COMMAND
NOP CAS latency = 2
4.2 Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2)
T1 T2 T3 T4 T5 T6 T7 T8
tDQW tDQZ
1 Clk Interval BANK A ACTIVATE
NOP
NOP
READ A
WRITE A
NOP
NOP
NOP
Must be Hi-Z before the Write Command
tCK2, I/O's
: "H" or "L"
DIN A0
DIN A1
DIN A2
DIN A3
T1
T2
T3
T4
T5
T6
T7
T8
DQM
tDQZ
OMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
NOP
NOP
CAS latency = 2
tCK1, I/O's
CAS latency = 3
DOUT A0
DOUT A1 Must be Hi-Z before the Write Command
DIN B0
DIN B1
DIN B2
tCK2, I/O's
: "H" or "L"
DOUT A0
DIN B0
DIN B1
DIN B2
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
19
V54C3128(16/80/40)4V(BGA)
6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
CILETIV LESOM
T0 CLK COMMAND
NOP
5. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
I/O's
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the Write are registered on the same clock edge.
Extra data is ignored after termination of a Burst.
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval
I/O's
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
20
V54C3128(16/80/40)4V(BGA)
7. Burst Write with Auto-Precharge Burst Length = 2, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
CILETIV LESOM
T0 CLK COMMAND
NOP CAS latency = 2
6.2 Write Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCK3, I/O's
DIN A0
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data must be removed from the I/O's at least one clock cycle before the Read dataAPpears on the outputs to avoid data contention.
COMMAND
BANK A ACTIVE
NOP
NOP
WRITE A
Auto-Precharge
NOP
NOP
NOP
NOP
NOP
tWR
CAS latency = 2
tRP
I/O's
CAS latency = 3
DIN A0
DIN A1
*
tWR
tRP
I/O's
DIN A0
DIN A1
Bank can be reactivated after trp
*
Begin Autoprecharge
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
21
V54C3128(16/80/40)4V(BGA)
CILETIV LESOM
T0 CLK COMMAND
NOP CAS latency = 2
7.2 Burst Read with Auto-Precharge Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
WRITE A
READ B
NOP
NOP tRP
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DOUT A0
DOUT A1
* *
DOUT A2
DOUT A3 tRP DOUT A2 DOUT A3
tCK3, I/O's
DOUT A0
DOUT A1
Bank can be reactivated after tRP
*
Begin Autoprecharge
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
22
V54C3128(16/80/40)4V(BGA)
8.2 Termination of a Burst Write Operation (CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
CILETIV LESOM
(CAS latency = 2, 3)
T0 CLK COMMAND
READ A CAS latency = 2
8.1 Termination of a Burst Read Operation
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
tCK2, I/O's
CAS latency = 3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
tCK3, I/O's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
COMMAND
CAS latency = 2,3
NOP
WRITE A
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
I/O's
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
23
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
9.1 AC Parameters for Write Timing
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCH CKE tCKS tCL tCS tCH tCK2
Begin Auto Precharge Bank A Begin Auto Precharge Bank B
tCKH
CS
RAS
CAS
WE 24 BA tAH AP tAS Addr
RAx CAx RBx CBx RAy RAy RAz RBy RAx RBx RAy RAz RBy
DQM tRCD tRC I/O
Hi-Z
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
tDS tDH
tDPL
tRP
tRRD
Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
9.2 AC Parameters for Read Timing
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Burst Length = 2, CAS Latency = 2
T10 T11 T12 T13
CLK tCH CKE tCKS CS tCL tCK2 tCS tCH
Begin Auto Precharge Bank B
tCKH
RAS
CAS
WE
BA tAH AP tAS Addr
RAx CAx RBx RBx RAy RAx RBx RAy
tRRD tRAS DQM tAC2 tRCD I/O
Hi-Z
Ax0 Ax1 Bx0 Bx1
tRC tAC2 tOH tHZ tRP tHZ
tLZ
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command
Precharge Command Bank A
Activate Command Bank A
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
\
25
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
10. Mode Register Set
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
2 Clock min.
CS
RAS
CAS
WE
BA
AP
Address Key
Addr
Precharge Command All Banks
Mode Register Set Command
Any Command
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
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26
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
11. Power on Sequence and Auto Refresh (CBR)
T0 T T T T T T T T T T1 T T T T T T T T T T T T
CLK
CKE
High level is required
Minimum of 2 Refresh Cycles are required
2 Clock min.
CS
RAS
CAS
WE
27
BA
AP
Address Key
Addr
DQM tRP I/O
Hi-Z
tRC
Precharge 1st Auto Refresh Command Command All Banks
2nd Auto Refresh Command
Mode Register Set Command
Any Command
Inputs must be stable for 200s
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
\
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
12. Power Down Mode
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCKSP CKE
CS
RAS
CAS
WE
28
BA
AP
RAx
Addr
RAx
DQM
Hi-Z
I/O
Activate Command Bank A
Precharge Command Bank A
Power Down Mode Entry
Power Down Mode Exit Any Command
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
\
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
13. Self Refresh (Entry and Exit)
T0 T1 T2 T3 T4 T5 T T T T T T T T T T T T T T T T T
CLK t CKSR tSREX
CKE
CS
RAS
CAS
WE
BA
AP
Addr tRC DQM
Hi-Z
I/O
All Banks must be idle
Self Refresh Entry
Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
29
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
14. Auto Refresh (CBR)
T0 T7
Burst Length = 4, CAS Latency = 2
T3 T4 T5 T6 T8 T9 T10 T11 T12 T17 T21
T1
T2
T13
T14
T15
T16
T18
T19
T20
T22
CLK tCK2 CKE
CS
RAS
CAS
WE BA
AP
RAx
Addr tRP tRC
(Minimum Interval)
RAx
CAx
DQM
Hi-Z
tRC
I/O
Ax0
Ax1
Ax2
Ax3
Precharge Command All Banks
Auto Refresh Command
Auto Refresh Command
Activate Command Bank A
Read Command Bank A
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
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30
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
15.1 Random Column Read (Page within same Bank) (1 of 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
CS
RAS
CAS
31
WE
BA
AP
RAw
RAz
Addr
RAw
CAw
CAx
CAy
RAz
CAz
DQM
Hi-Z
I/O
Aw0
Aw1
Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Az1
Az2
Az3
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
\)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
15.2 Random Column Read (Page within same Bank) (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
CS
RAS
CAS
WE
BA
AP
RAw
RAz
Addr
RAw
CAw
CAx
CAy
RAz
CAz
DQM
Hi-Z
I/O
Aw0
Aw1
Aw2
Aw3
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
\)
32
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
16.1 Random Column Write (Page within same Bank) (1 of 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Burst Length = 4, CAS Latency = 2
T17
T18
T19
T20
T21
T22
CLK tCK2 CKE
CS
RAS
CAS
WE
BA
AP
RBz
RBz RAw
Addr
RBz
CBz
CBx
CBy
RBz RAw
CBz CAx
DQM
Hi-Z
I/O
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
\)
33
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
16.2 Random Column Write (Page within same Bank) (2 of 2)
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
CS
RAS
CAS
34
WE
BA
AP
RBz
RBz
Addr
RBz
CBz
CBx
CBy
RBz
CBz
DQM
Hi-Z
I/O
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
\)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK tCK2 CKE
High
CS
RAS
CAS
WE
35
A11(BS)
A10
RBx
RAx
RBy
A0 - A9
RBx
CBx
RAx
CAx
RBy
CBy
DQM
Hi-Z
tRCD
tAC2
tRP
I/O
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Command Bank B Read Command Bank A
Activate Command Bank B
Read Command Bank B
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
17.1 Random Row Read (Interleaving Banks) (1 of 2)
Burst Length = 8, CAS Latency = 2
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK tCK3 CKE
High
CS
RAS
CAS
WE
A11(BS)
A10
RBx
RAx
RBy
A0 - A9
RBx
CBx
RAx
CAx
RBy
CBy
DQM
Hi-Z
tRCD
tAC3
tRP
I/O
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
17. 2 Random Row Read (Interleaving Banks) (2 of 2)
Burst Length = 8, CAS Latency = 3
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
36
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK tCK2 CKE
High
CS
RAS
CAS
WE
A11(BS)
A10
RAx
RBx
RAy
A0 - A9
RAx
CAX CAy
RBx
CBx
RAy
CAy
tRCD DQM
Hi-Z
tDPL
tRP
tDPL
I/O
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B Precharge Command Bank A
Activate Command Bank A
Write Command Bank A Precharge Command Bank B
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
18.1 Random Row Write (Interleaving Banks) (1 of 2)
Burst Length = 8, CAS Latency = 2
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
37
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK tCK3 CKE
High
CS
RAS
CAS
WE
A11(BS)
A10
RAx
RBx
RAy
A0 - A9
RAx
CAX
RBx
CBx
RAy
CAy
tRCD DQM
Hi-Z
tDPL
tRP
tDPL
I/O
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
18.2 Random Row Write (Interleaving Banks) (2 of 2)
Burst Length = 8, CAS Latency = 3
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
38
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
19.1 Precharge Termination of a Burst (1 of 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
Burst Length = 8, CAS Latency = 2
T15 T16 T17 T18 T19 T20 T21 T22
CLK tCK2 CKE
High
CS
RAS
CAS
WE
39
BA
AP
RAx
RAy
RAz
Addr
RAx
CAx
RAy
CAy
RAz
CAz
tRP DQM
Hi-Z
tRP
tRP
I/O
DAx0 DAx1 DAx2 DAx3
Ay0
Ay1
Ay2
Az0
Az1
Az2
Activate Command Bank A
Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked.
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Read Burst.
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
19.2 Precharge Termination of a Burst (2 of 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
Burst Length = 4, 8, CAS Latency = 3
T16 T17 T18 T19 T20 T21 T22
CLK tCK3 CKE
High
CS
RAS
CAS
WE
40
BA
AP
RAx
RAy
RAz
Addr
RAx
CAx
RAy
CAy
RAz
tRP DQM
Hi-Z
tRP
I/O
DAx0
Ay0
Ay1
Ay2
Activate Command Bank A
Write Command Bank A Write Data is masked
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A Precharge Termination of a Read Burst.
Precharge Termination of a Write Burst.
CILETIV LESOM
V54C3128(16/80/40)4V(BGA)
V54C3128(16/80/40)4V(BGA)
CILETIV LESOM
CURRENT STATE1
Idle H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L
Complete List of Operation Commands SDRAM Function Truth Table
CS RAS
X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L L
CAS
X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H H L
WE
X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L H L X
BS
X X BS BS BS BS X OpX X BS BS BS BS X X X BS BS BS BS BS X X X BS BS BS BS BS X X X BS BS X BS BS X
Addr
X X X X RA AP X Code X X CA,AP CA,AP X AP X X X X CA,AP CA,AP X AP X X X X CA,AP CA,AP X AP X X X X X X X AP X
ACTION
NOP or Power Down NOP ILLEGAL2 ILLEGAL2 Row (&Bank) Active; Latch Row Address NOP4 Auto-Refresh or Self-Refresh5 Mode reg. Access5 NOP NOP Begin Read; Latch CA; DetermineAP Begin Write; Latch CA; DetermineAP ILLEGAL2 Precharge ILLEGAL NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop Command > Row Active Term Burst, New Read, DetermineAP3 Term Burst, Start Write, DetermineAP3 ILLEGAL2 Term Burst, Precharge ILLEGAL NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop Command > Row Active Term Burst, Start Read, DetermineAP3 Term Burst, New Write, DetermineAP3 ILLEGAL2 Term Burst, Precharge3 ILLEGAL NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL
Row Active
Read
Write
Read with Auto Precharge
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
41
V54C3128(16/80/40)4V(BGA)
CILETIV LESOM
CURRENT STATE1
Write with Auto Precharge H L L L L L L L H L L L L L L H L L L L L L H L L L L L L H L L L L L H L L L L
SDRAM FUNCTION TRUTH TABLE(continued)
CS RAS
X H H H H L L L X H H H L L L X H H H L L L X H H H L L L X H H H L L X H H H L
CAS
X H H L L H H L X H H L H H L X H H L H H L X H H L H H L X H H L H L X H H L X
WE
X H L H L H L X X H L X H L X X H L X H L X X H L X H L X X H L X X X X H L X X
BS
X X BS BS X BS BS X X X BS BS BS BS X X X BS BS BS BS X X X BS BS BS BS X X X X X X X X X X X X
Addr
X X X X X X AP X X X X X X AP X X X X X X AP X X X X X X AP X X X X X X X X X X X X
ACTION
NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after tRP NOP;> Idle after tRP ILLEGAL2 ILLEGAL2 ILLEGAL2 NOP4 ILLEGAL NOP;> Row Active after tRCD NOP;> Row Active after tRCD ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL NOP NOP ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after tRC NOP;> Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL
Precharging
Row Activating
Write Recovering
Refreshing
Mode Register Accessing
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
42
V54C3128(16/80/40)4V(BGA)
CILETIV LESOM
STATE(n)
Self-Refresh6
Clock Enable (CKE) Truth Table:
CKE n-1
H L L L L L L H L L L L L L H H H H H H H H L
CKE n
X H H H H H L X H H H H H L H L L L L L L L L
CS
X H L L L L X X H L L L L X X H L L L L L L X
RAS
X X H H H L X X X H H H L X X X H H H L L L X
CAS
X X H H L X X X X H H L X X X X H H L H L L X
WE
X X H L X X X X X H L X X X X X H L X X H L X
Addr
X X X X X X X X X X X X X X X X X X X X X X X
ACTION
INVALID EXIT Self-Refresh, Idle after tRC EXIT Self-Refresh, Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID EXIT Power-Down, > Idle. EXIT Power-Down, > Idle. ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low-Power Mode) Refer to the function truth table Enter Power- Down Enter Power- Down ILLEGAL ILLEGAL ILLEGAL Enter Self-Refresh ILLEGAL NOP
Power-Down
All. Banks Idle7
Abbreviations:
RA = Row Address CA = Column Address BS = Bank Address AP = Auto Precharge
Notes for SDRAM function truth table: 1. 2. 3. 4. 5. 6. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank. Must satisfy bus contention, bus turn around, and/or write recovery requirements. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP). Illegal if any bank is not Idle. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 8. Must be legal command as defined in the SDRAM function truth table.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
43
V54C3128(16/80/40)4V(BGA)
CILETIV LESOM
Package Diagram
60-Pin WBGA
8.500.10 1.05 1.60 0.80 0.50 A
O0.450.05 O0.15 O0.08
0.20 M S B
13.0 0.10
MSAB MS
1.00
1.00 B Out of die mark area (#2) // 0.2 9 S
0.20 M S A
0.25+0.05 (#1) -0.10 0.12 S Min 0.10 (#1)
Notes: 1. No bond figure exposed 2. Do not measure / / within this area
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
44
WORLDWIDE OFFICES
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V54C3128(16/80/40)4V(BGA)
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
CILETIV LESOM
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U.S. SALES OFFICES
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(c) Copyright 2001, MOSEL VITELIC Inc.
9/01 Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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